A conventional computer uses the Von Neumann architecture, and in the architecture, computation and storage are separated, and are respectively completed by a central processing unit (CPU) and a memory. With development of science and technology, speeds and capacities of the CPU and the memory are rapidly increased; however, improvement of a speed of a bus used for transmitting data is limited, which results in a transmission bottleneck called a Von Neumann bottleneck, that is, a memory wall. Therefore, it is expected that computation and storage can be completed in a same component or circuit, so as to implement integration of information storage and computation and increase a speed and efficiency. A resistive random access memory (RRAM) serves as a next-generation non-volatile memory with high potential, and can implement reversible conversion between high resistance and low resistance under the action of an electrical impulse, and a high resistance state and a low resistance state are used to store “0” and “1”.
In the prior art (Chinese Patent Application Publication 102882514 A), an AND logic circuit is extended to become a computational array. A basic circuit implements a logical operation by introducing an auxiliary input section and a comparator. However, an operation method for implementing computation is relatively complex, and a computation result still needs to be output to a dedicated external memory for storage.